1. Field of the Invention
The present invention is generally in the field of semiconductors. More particularly, the invention is in the field of the fabrication of memory cells.
2. Background Art
Memory cells and logic field-effect transistors (FETs) are widely utilized in electronic systems for cell phones, computers, and other electronic devices. The memory cells and the logic FETs can be fabricated on separate semiconductor dies. However, it is desirable to integrate memory cells with logic FETs in a common substrate in a system-on-chip (SoC) for increased performance, lower manufacturing cost, and system reconfigurability. It is further desirable to integrate memory cells and logic FETs in an SoC by utilizing advanced process technologies, such as 45.0 nanometer (nm) and smaller process technologies.
In advanced process technologies, logic FETs typically include a gate that can be fabricated by utilizing a high dielectric constant (high-k) metal gate process to achieve gate oxide scaling. Integrating memory cell fabrication with the high-k metal gate process to fabricate the memory cells with the logic FETs can require additional masks and process steps. For example, memory cells, such as flash memory cells, can include a floating gate and an overlying control gate, where the floating gate and the control gate are fabricated by utilizing a polysilicon (e.g., poly-SioN) gate process. As such, additional masks and process steps are required to integrate flash memory cells, fabricated by utilizing the polysilicon gate process, and logic FETs, fabricated by utilizing the high-k metal gate process, in an SoC. This is inefficient and can undesirably increase manufacturing cost.
Thus, there is a need in the art for efficiently fabricating memory cells with logic FETs.